Digital signal processors (DSP) designed for a range of applications and having a wide variety of architectures, commonly employ a number of peripheral device functions. FIG. 1 illustrates a conventional DSP architecture. In this example, DSP core 101 communicates with program/data memory 102 using M bus 100. M bus 100 is a complex bus that includes program read, data read and data write busses. Bus arbitration unit 106 receives signals from M bus 100 via lines 108, supplies signals 112 to program/data memory 102 and communications bi-directionally with DSP core 101 via control/acknowledge lines 107. A separate peripheral bus P bus 114 allows for data transfers among on-chip memory 102, multi-channel buffered serial ports 105 and host port interface (HPI) 115. Direct memory access (DMA) controller 113 manages these data transfers. Multi-channel buffered serial ports 105 also have a direct communication link with DSP core 101 and program/data memory 102. A configuration bus 103 provides DSP core 101 with access to configure peripherals such as DMA controller 113, multi-channel buffered serial ports 105, watchdog timer 109, general purpose timers 104 and general purpose I/O 110. Configuration bus 103 provides DSP core 101 with access to poll status information from all the on-chip peripherals. Configuration bus 103 allows DSP core 101 to input data to and output data from the peripherals such as multi-channel buffered serial ports 105 and general purpose I/O 110. RHEA bridge 111 allows DSP core 101 access to the configuration bus 103. The use of timer functions allows programmers to exercise control of system operation in a variety of critical circumstances.
FIG. 2 illustrates general purpose timer 110. General purpose timer 110 operates under the control of the 16-Bit timer control register (TCR) 235 described in. Table 1. Two fields of timer control register 235, timer divide down ratio (TDDR) 232 and pre-scalar count (PSC) 233, are the most pertinent for consideration here.
TABLE 1BitsDescription15-12Reserved11Soft: breakpoint related10Free: breakpoint related9-6PSC: Pre-Scalar Count5TRB: Timer Reload Control4TSS: Timer Stop Status3-0TDDR: Timer-Divide-Down Ratio
The general purpose timer clock 222 is generated in buffered form from CPU clock 226. General purpose 110 timer consists of two major blocks. The first major block is main timer block 200, consisting of timer period register (PRD) 201, timer register/down counter (TIM) 203, state ‘0’ decoder 204 and general purpose timer output block 205. The second major block is pre-scalar 210, consisting of timer control register (TCR) 235, 4-bit pre-scalar register/down counter 223, state ‘0’ decoder 214 and pre-scalar clock output block 215. A 4-bit register (PSC) 233 holds bits 9-6 of timer control register (TCR) 235. The timer initialization causes register (PSC) 233 to be loaded with the contents of the timer divide down ratio (TDDR) bits 234 (bits 3-0) of the timer control register (TCR) 235. These four PSC bits 234 are loaded into the pre-scalar register/down counter (PSR/DC) 223 on detection of a ‘0’ state in pre-scalar register/down counter 223 itself. The state ‘0’ decoder 214 generates an active low clock gating signal for loading register 223 via OR gate 221.
Under normal operation, timer register/down counter 203 is loaded with the period value 209 of timer period register 201 on the same clock when timer register/down counter 203 decrements to ‘0’. The period value (PDR) 209 is also loaded into timer register/down counter 203 when the device is reset from reset input (SRESET) 218, or when the timer is individually reset from timer reset signal (TRB) 219. The main output of general purpose timer 104 is the timer interrupt (TINT) signal 230. This is sent to DSP core 101 via buffer 229 which forms timer output (TOUT) signal 228. The duration of a timer output signal 228 pulse is equal to the period of CPU clock 226.
Pre-scalar block 210 has two elements similar to time period register 201 and timer register/down counter 203. These are timer divide down ratio register (TDDR) 231 and pre-scalar register/down counter (PSR/DC) 223. Both timer divide down ratio register(TDDR) 231 and pre-scalar register/down counter (PSR/DC) 223 are fields in the timer control register 235. Under normal operation pre-scalar register (PSC) 233 is loaded with the value of the contents of timer divide down ratio register (TDDR) 231 when pre-scalar register/down counter (PSR/DC) 223 decrements to zero. This encoded timer divide down ratio value is also loaded into pre-scalar register/down counter (PSR/DC) 223 when the device is reset via reset signal (RESET) 218 or when the timer is individually reset via timer reset signal 219. Pre-scale register/down counter 223 is clocked by general purpose timer clock 222 derived from CPU clock 226 subject to the control of timer gating bit 227. Each CPU clock 226 decrements pre-scalar counter register 223 by one.
General purpose timer 104 can be stopped using timer gating bit 227 to turn off the clock input via AND gate 225. Stopping the operation of general purpose timer 104 allows the device to run in a low-power mode when the timer is not needed.
The rate of timer interrupt (TINT) signal 230 is equal to the frequency of CPU clock 226 divided by two independent factors:       TINT    ⁢                   ⁢    rate    =            1                                    t            c                    ⁡                      (            C            )                          ⁢                                   ⁢                  (          u          )                ×                  (          v          )                      =          1                                    t            c                    ⁡                      (            C            )                          ⁢                                   ⁢                  (                      TDDR            +            1                    )                ⁢                                   ⁢                  (                      PRD            +            1                    )                    where: tc(c) is the period of CPU clock 226; u is the sum of the timer divide down ratio contents plus 1; and v is the sum of timer period register (PRD) 201 contents plus 1.
The current value in the timer can be read by reading timer register/down counter 203. Pre-scalar counter register 223 can be read by reading timer control register 235. Because it takes two instructions to read both registers, there may be a change between the two reads as the counter decrements. Therefore, when precise timing measurements are needed, it is more accurate to stop the timer before reading these two values. The timer can be stopped by setting timer gating bit 227 and re-started by clearing timer gating bit 227.
General purpose timer 104 can be used to generate a sample clock for peripheral circuits such as an analog interface. This can be accomplished by using timer output signal 228 to clock a device or by using timer interrupt (TOUT) signal 230 to periodically read a register.
General purpose timer 104 is initialized with the following steps:                1) Stop the timer by writing a ‘1’ to timer gating bit 227 in timer control register (TCR) 235.        2) Load time period register 201.        3) Initialize the timer by reloading timer control register 235 to initialize timer divide down ratio. 231 Enable the timer by setting timer gating bit 227 to ‘0’ and timer reset signal 219 to ‘1’ to reload the timer period.        
Optionally, assuming INTM=‘1’, the timer interrupt may be enabled by:                1) Clearing any pending timer interrupts.        2) Enabling the timer interrupt.        3) Enabling interrupts globally, if necessary.        
At reset, timer register/down counter 203 and timer period register 201 are set to a maximum value of hexadecimal ‘FFFF’. A timer divide down ratio (TDDR) field of timer control register 235 is cleared to zero and the timer is started.